(1) Field of the Invention
This invention relates specifically to chemical-mechanical polishing (CMP) methods used to planarize device wafers having multiple levels of polysilicon layers sandwiched between insulating layers.
(2) Background of the Invention & Description of Prior Art
In the development of the integrated circuits (IC), the industry is ever striving to improve performance by scaling down the device dimensions for high speed circuits. However, scaling down the device has arrived at a point that further scaling is less profitable due to the high risk of yield and reliability failures. Eventually, the down-sizing of the active device have become less expedient in improving the performance further, without exponentially increasing the cost of fabrication by the IC manufacturers. Thereby, the manufacturers of the IC industry seek other alternatives to increase the circuit speed and maximum functional density and complexity by improving the interconnects. The predominant method to circumvent the aforementioned limitations involves the adaptation of vertical stacking of integrated devices and interconnect wiring levels.
The switch to multilevel interconnection for performance advantage causes loss of topographical planarity. The resulting non-planar topography of the device wafer in turn creates problems in photolithography, etching, as well as electrical shorts and many other related problems. One of the current state-of-the-art methods to planarize the non-planar surface of device wafer is by the chemical-mechanical polishing (CMP) technique.
Doan & Meikle in U.S. Pat. No. 5,395,801 have described a method for planarizing a semiconductor wafer having non-planar topography by the deposition of a conformal layer of insulating material of a first thickness to the wafer. A CMP protective layer of different composition and thickness than the conformal insulating layer is deposited over the conformal layer. The CMP polishing of both protective and underlying conformal insulating layers is done with a single CMP step using a single CMP slurry and under conditions which in combination with the slurry removes the conformal layer material at a faster rate than the protective layer material, the protective layer upon outward exposure of conformal insulating layer in high topographical areas restricting material removal from low topographical areas during this CMP process. Doan & Meikle further described other alternatives to the aforementioned single slurry CMP process by using two or three CMP steps with respective CMP slurries and different selective polishing rates.
This invention will describe a CMP process to address the problems of multi-level polysilicon to polysilicon shorts due to conventional CMP planarization of the non-planar surface of semiconductor device wafer, by deposition of another insulating layer after the chemical-mechanical polishing before depositing the next polysilicon layer.